Integrated circuits may generally be categorized into various groups such as microprocessors, memories, programmable logic devices, and application specific integrated circuits (ASICs). With the semiconductor industry continually driven to reduce a product cost coupled with shorter product life spans, manufacturers have been under tremendous pressure to reduce research and development (R&D) costs for new products. Programmable logic products have gained momentum and have out-grown the ASIC business. In the early phases of development, programmable logic products provide design alternatives for new products through a flexibility in configuration implementation.
Programmable structures such as a programmable logic device (PLD) or a field programmable gate array (FPGA) are classes of integrated circuits that can be programmed by a user to implement logic functions. These functions are determined by the fuse connections or “fuses” loaded in a device configuration process. The fuses (also called configuration bits) may be stored inside or outside the chip. The fuse configuration is either read out from a memory and shifted into latching elements within the chip or read directly from a non-volatile memory array within the chip. For instance, the fuses can be programmed or erased by an embedded high voltage circuit with a non-volatile memory array. Unlike customized hard-wired chips or ASICs, the programmable device can be easily programmed as well as reprogrammed by changing the fuses to perform a totally different logic function.
A capability of repeated programming makes programmable logic devices well suited for new product development. In a development cycle, engineers iteratively try new ideas in an integrated circuit implementation and verify that the results meet a design specification. Having a fast and easy way to implement a design concept in a programmable chip can make the iterative development cycle more efficient and productive.
The configuration data for an FPGA is stored in a separate chip called a configurator. The configurator contains non-volatile memory and logic control circuitry. When a system is powering-up, the configurator's contents are download into storage cells which are usually made of static latches within the FPGA. When powered off, an FPGA loses all configuration data stored in latches.
A PLD stores the “fuses” in a non-volatile memory array within the PLD chip. When a PLD powers up, a portion of the fuses are loaded into a series of latches and provide the necessary control of the functionality. Part of the fuses remain in the non-volatile memory array. When the chip starts functioning, the information is read out through a sense amplifier to meet speed requirements. Sense amp based fuse loading consumes a large amount of current. Recent PLD designs have incorporated a complete set of configuration latches to receive the entire set of configuration bits from the non-volatile memory array at power-up to avoid sense amp loading.
Configuration fuses can also be loaded externally from another microcontroller. Externally loaded fuses are available in addition to the previously fixed fuses loaded at system power-up or in a configurator. Externally loaded fuses offer a key flexibility for changing the functionality of a programmable logic device. The external fuses can be used to update a portion or all of the functionality of the programmable device. New functionality can be rapidly loaded and the new behavior can be tested and verified for acceptance as a new device configuration. Loading configurations with an external microcontroller also avoids the inconvenience and power consumption of going through the programming sequence of a non-volatile memory each time a new configuration is considered.
Various attempts to improve a management of programmable logic device configurations can be found. For example, U.S. Pat. No. 5,426,378, to Ong, discloses two banks of configuration memory being multiplexed to allow a device to operate with alternating configurations during a user clock cycle. U.S. Pat. No. 5,291,079, to Goetting, discloses capturing logical state data on interconnect lines with a configuration control unit and shifting the data out to a configuration register. Additional examples include U.S. Pat. No. 6,351,139, to Ighani et al., which discloses a scheme for reading and writing configuration bit data to a memory and for verification of configuration bits. U.S. Pat. No. 6,255,848, to Shultz et al., discloses configuration data bit values being transmitted on a bi-directional bus and stored in an internal shift register. Further, U.S. Pat. No. 5,808,942, to Sharpe-Geisler, proposes a new static random access memory (SRAM) cell that provides write and read capability through an internal data path using a reduced number of transistors per cell.
However, certain desirable features are neither described nor taught in the prior art. For instance, a capability to write-back a device configuration to an internal or external memory or a capability to load new configuration data or shift-out a present configuration and maintain a continuous operation of the configured programmable device are not mentioned.
The competitive pressure for new products and the ability to rapidly configure programmable logic devices to meet new product demands is a natural match. The short life span of a product adds an incentive to quickly produce a new functionality for a product. Many times the new functionality needed for a next generation product to be competitive is only an incremental amount of change compared to the previous generation. To rapidly apply a new configuration and produce a product that remains competitive in a market place is highly desirable capability for a company. Within a programmable device, the ability to mix and match features and functionality between the present configuration and that of a developmental configuration in an external configurator is one way to produce the desired capability.
What is needed is a way to rapidly complete a design and verification cycle of a proposed configuration for a new programmable logic device. In producing such a cycle, there would be an advantage to rapidly shift-out a desired new configuration after an iteration of loading and verifying a proposed configuration. An ability to capture successive configurations within the design process means that configuration milestones can be managed and a path to the next generation product rapidly achieved. An ability to quickly shift-out a given design configuration, as part of a development cycle, would accomplish such a result. Additionally, there is a desirability to apply the writing-back of configurations to either an external or internal configurator as well as to an external development configuration memory. With an added write-back capability a developer of a new functionality for a programmable logic device would be able to easily develop, verify, and retain a desired configuration.